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|Title: ||Computer aids for the design of large scale integrated circuits.|
|Authors: ||Swan, George Baxter|
|Supervisors: ||Eades, J. D.|
|Issue Date: ||Dec-1983|
|Publisher: ||Robert Gordon University|
|Citation: ||SWAN, G.B., 1982. Computer aids for the design of large scale integrated circuits. Royal Television Society Journal, May 1982.|
SWAN, G.B. and EADES, J.D., 1984. CADIC: an efficient integrated circuit design aid. CAD84 conference, Brighton, March 1984.
|Abstract: ||The work described in this thesis is concerned with the development
of CADIC (Computer Aided Design of Integrated Circuits), a suite of
computer programs which allows the user to design integrated circuit
layouts at the geometric level.
Initially, a review of existing computer aids to integrated circuit
design is carried out. Advantages and disadvantages of each computer
aid is discused, and the approach taken by CADIC justified in the light
of the review.
The hardware associated with a design aid can greatly influence its
performance and useability. For this reason, a critical review of
available graphic terminals is also undertaken.
The requirements, logistics, and operation of CADIC is then
discussed in detail. CADIC provides a consise range of features to aid
in the design and testing of integrated circuit layouts. The most
important features are however CADIC's high efficiency in processing
layout data, and the implementation of complete on-line design rule
checking. Utilization of these features allows CADIC to substantially
reduce the lengthy design turnaround time normally associated with
manual design aids.
Finally, the performance of CADIC is presented. Analysis of the
results show that CADIC is very efficient at data processing, especially
when small sections of the layout are considered. CADIC can also
perform complete on-line design rule checking well within the time it
takes the designer to start adding the next shape.|
|Appears in Collections:||Theses (Engineering)|
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